Enhanced Hardware Trojan Detection And Deactivation The Trojan Circuit

Abstract

Global interconnection has allowed Integrated Circuit (IC) designers to greatly reduce costs by subcontract their manufacturing needs to external fabricators. However, there is a low cost Fabless semiconductor facilities have introduced a new potential for security viruses. Standardized testing and verification procedures cannot guarantee the circuit being tested is precisely the circuit that was designed.  Thus, an adversary may insert malicious circuits known as hardware Trojans. Trojan trigger to observe either a faulty output or measurable uncommon on side-channel signals or disable functionality, reduce performance, leak Hidden keys, insert a backdoor within the designed circuit.  Transition is modeled by geometric distribution and the number of clock cycles required to generate a transition is estimated. Existing system, a dummy scan flip-flop insertion procedure is proposed aiming at decreasing transition generation time. The procedure increases transition probabilities of nets beyond a specific threshold but this paper presents new hardware trust architecture to magnify functional Trojans activity. In this paper architecture modification done by introducing an LFSR and detecting the Trojan threats there by deactivate Trojan threats