FPGA Implementation Of Highly Efficient Parallel Hardware Architecture For AES-GCM

Abstract

The Advanced Encryption Standard (AES) is a symmetric-key encryption algorithm and it provides standardized authentication by using Galois/Counter Mode (GCM). Hence it is utilized in various security-constrained applications. Many of the AES-GCM applications are power and resource constrained and requires efficient hardware implementations. In this paper, different Application-Specific Integrated Circuit (ASIC) architectures of building blocks of the AES-GCM algorithms are evaluated and optimized to identify the high-performance and low-power architectures for the AES-GCM.  In AES, to obtain the least complexity S-box (Sub-Bytes), the formulations for the Galois Field (GF) subfield inversions in GF (2⁴) are optimized. By conducting exhaustive simulations for the input transitions, the average and peak power consumptions of the AES S-boxes  can be analysed by  considering the switching activities, gate-level netlists, and parasitic information and  the S-box realisation based on lookup tables (LUTs) could be area efficient when implemented utilizing the memory resources available on FPGAs.  The proposed parallel method uses two GF (2¹²⁸⁾ multipliers and it results high-throughput and low latency GCM hardware architectures which is suitable for high-performance applications.