Efficient Reduction of Area and Delay in Null Convention Logic Design Paradigm

Abstract

Synchronous circuit designs face many challenges such as clock skew, clock jitter and power consumption. Asynchronous clockless circuit design is a solution to these clock issues. Asynchronous circuits have merits of low power, anti-interference, high robustness, and module reusability due to its clockless nature. NULL Convention Logic (NCL) is one of the promising candidates for asynchronous circuit design paradigms. NCL circuits are said to be correct-by-construction and delay insensitive circuits. In this paper, a new methodology for mapping multi-rail logic expressions to NULL convention logic (NCL) gate library is proposed to reduce area and delay of NCL circuits when compared to the existing algorithm.