VHDL Design and Simulation of a 32 Bit MIPS RISC Processor

Abstract

Today's smart phones, tablets, cameras, routers and play stations make use of MIPS RISC technology due to several key advantages. Due to the presence of the reduced instruction set, the processing time of the processor is reduced. It has improved flexibility and adaptability, is faster and inexpensive. So, here we are designing a microprocessor without interlocked pipelining stages i.e. MIPS RISC Processor using Xilinx software. For that firstly we are designing the Read only memory, i.e. ROM and then the random access and then we have designed the instruction fetch unit.