Evaluation Of 3D Network-On-Chip Architectures By Using Layers


Dr. T. Gnanaskaran
P. Kalyanasundaram
Dinesh Kumar


SoC are widely used in high volume and high end application . Due to the exponential growth of the transistor the 2D chip fabrication technology is facing a lot of challenges. The NoC concept replaces design-specific global on chip wires with a generic on-chip interconnection network realized by specialized routers that connect generic processing elements . The architectural level, Networks on- Chip (NoC) has been proposed to address the complexity of interconnecting an ever-growing number of Intellectual Property (IP) blocks like DSP, Memories, I/O Ports, and Peripherals . 3D NoC is a promising choice for implementing scalable interconnection architectures. A design methodology that integrates floor planning where the IP blocks are implemented, routers assignment, and cycle-accurate NoC simulation is proposed to evaluate the performance of the 3D NoC. Let us consider 3D NoC where IP blocks are implemented in top and bottom layers and 3D NoC routers are implemented in the middle layer using mesh topology. The implementation of the 3D NoC routers on a separate layer offers an additional area that may be utilized to improve the network performance by increasing the number of virtual channels, buffers size, and mesh size. The scalability and predictability of NoCs enable designers to design increasingly complex systems, with large numbers of IP/cores and lower communication latencies for many applications.  Experimental results show that increasing the number of virtual channels rather than the buffers size has a higher impact on network performance. Increasing the mesh size can significantly improve the network. The 3-layer architecture can offer significantly better network performance compared to the 2D architecture.